The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode through a gate contact controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions.
With the increased downscaling of the transistor structures, a number of parasitic capacitances are introduced into the device which can effectively reduce the speed (in terms of working frequency) of future and present technologies. This issue may be most pronounced for three dimensional device architectures such as fin-based or wire-based multi-gate transistors. A main concern is the parasitic capacitance between the source and drain regions, and the gate contacts, which is desirably drastically reduced.
Accordingly, it is desirable to provide integrated circuits with a reduced parasitic capacitance. It is also desirable to provide improved integrated circuits with respect to a ring oscillation and improved integrated circuit speed and performance. Furthermore it is desirable to provide a process for making integrated circuits that is easily integrateable into existing process lines. Additionally, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.